1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device. In particular, the invention relates to a semiconductor device in which a plurality of wafers are laminated together and a method of manufacturing a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2008-035163, filed on Feb. 15, 2008, the content of which is incorporated herein by reference.
2. Description of Related Art
A three-dimensional semiconductor integrated circuit device having a configuration in which two or more wafers are laminated and are electrically connected to each other through an embedded wiring line is known in the related art. For example, Japanese Unexamined Patent Application, First Publication No. 2007-59769 (hereinafter Patent Document 1) discloses a semiconductor device that forms a desired semiconductor circuit by laminating a plurality of substrates together and electrically connecting semiconductor circuit portions formed on the substrates. In the semiconductor device disclosed in the Patent Document 1, a semiconductor circuit portion of an upper substrate and a semiconductor circuit portion of a lower substrate are electrically connected to each other by being laminated in a state where a penetrating wiring portion exposed from a bottom surface of the upper substrate and a bump of a principal surface of the lower substrate are in contact with each other.
However, in the known semiconductor device in which a plurality of wafers are laminated together, the plurality of wafers are electrically connected to each other through an electric signal connecting portion, such as a bump or a penetrating wiring portion protruding from a lamination surface. Specifically, in the technique disclosed in the Patent Document 1, the upper substrate and the lower substrate are electrically connected to each other through the penetrating wiring portion protruding from the bottom surface of the upper substrate and the bump protruding from the principal surface of the lower substrate.
When electrically connecting the plurality of wafers through the electric signal connecting portion protruding from the lamination surface as described above, the electric signal connecting portion was often damaged in laminating the wafers together. If the electric signal connecting portion is damaged, the electrical stability or reliability in the electric signal connecting portion becomes insufficient or the mechanical characteristics of the semiconductor device become unstable. Accordingly, there was a possibility that a semiconductor device with stable performance could not be obtained.
In view of the above situation, it is an object of the invention to provide a semiconductor device which is able to effectively prevent damage occurring in an electric signal connecting portion protruding from a lamination surface in laminating a plurality of wafers together and which has excellent reliability and stable performance.
In addition, it is another object of the invention to provide a method of manufacturing a semiconductor device which is able to effectively prevent damage occurring in an electric signal connecting portion protruding from a lamination surface in laminating a plurality of wafers together and which has excellent reliability and stable performance.